1. Field of the Invention
This invention relates to an electrically erasable programmable read only memory (EEPROM) device. More particularly, this invention relates to an improved EEPROM device having higher breakdown voltage and lower defect density, including reduced charge trapping in oxide layers and a method of making same.
2. Description of the Prior Art
In the construction of some types of EEPROMs of the MOS type, for example, using Fowler-Nordheim tunneling, an additional gate, called a floating gate, is placed between the control gate and the substrate. This floating gate is used to store a charge which changes the threshold voltage of the device. This charge must be erased or removed for the transistor to become operable under the normal bias of the control gate. The two gates are separated by a layer of oxide called an interlevel oxide. Another layer of oxide, known as a tunnel oxide, is placed between the floating gate and the underlying substrate. This tunnel oxide layer is usually less than 100 Angstroms in thickness. While MOS devices initially were constructed using, respectively, metal, oxide, and silicon layers, the metal layer has been conventionally replaced with polycrystalline silicon (polysilicon) which is doped to enhance the conductivity of the polysilicon material.
For most MOS devices, wherein the usual gate oxide layer is about 250-300 Angstroms in thickness, the use of polysilicon for the gate electrode is very satisfactory. However, when the oxide layer is very thin, as in the above described tunnel oxide layer beneath the floating gate of an EEPROM device, the uneven interface formed between the polysilicon and the thin tunnel oxide can result in unacceptably low breakdown voltages in such devices. This may be caused by virtue of the crystalline nature of the polysilicon.
This problem is best shown in the prior art illustrations of FIGS. 1A and 1B. In FIG. 1A, a silicon substrate 10, having a smooth surface, has formed thereon a thin layer of oxide 14. A layer of polysilicon 18 is deposited over oxide layer 14. As shown in exaggerated form in FIG. 1A, the lower surface 17 of polysilicon layer 18 abutting oxide layer 14 is not smooth. While the upper surface 19 of polysilicon layer 18 could be polished smooth, basically little can be done about the uneven undersurface 17.
When the structure is exposed to subsequent processing steps, including heating of the structure, oxide growth on polysilicon surface 17 as well as diffusion at the polysilicon/oxide interface can result in the structure shown in FIG. 1B wherein the uneven surface 17 of polysilicon layer 18 has been replaced by the uneven interface 16 between oxide layer 14 and polysilicon layer 18. The result is an uneven oxide thickness between silicon substrate 10 and polysilicon 18 which can allow intense electrical fields to exist in the oxide at the thinnest points and eventually cause unacceptable current leakage or breakdown across the tunnel oxide of such a device.
The use of polysilicon as the electrode requires the addition of a dopant to the polysilicon to achieve the desired conductivity. Conventionally, phosphorus oxychloride (POCl.sub.3) is used to dope the polysilicon to provide a N+ type layer. However, the doping material sometimes migrates from the polysilicon into the underlying tunnel oxide which can affect oxide integrity. This causes charge trapping which will interfere with the erasable feature of the EEPROM device, and also affects the breakdown voltage of the structure. This charge migration may be due to the high concentration of the phosphorus oxychloride dopant as well as the inability to accurately control the concentration of the dopant.
It would therefore be desirable to provide an integrated circuit structure of the EEPROM type having a floating gate which will have a smoother interface between the tunnel oxide and the floating gate and which will have a lower migration of dopant into the adjoining tunnel oxide layer to reduce the occurrence of charge trapping and a method of fabricating such a structure.